The present invention relates to information processing systems including multiple processors linked to multiple memory cards of main storage through a shared interface, and more particularly to a means for modifying data stored in main memory, with minimal impact upon the interface.
In recent years and throughout the computer industry, the performance of information processing devices has improved rapidly, particularly in terms of more rapid performance of data processing operations. Data processing systems increasingly employ multiple processing devices sharing a common interface for carrying out data transmissions between the processors and main storage which typically is composed of multiple memory cards. Improvements in memory subsystems have not kept pace with the improvements in processors, particularly when configurations of multiple, parallel processors are considered. Accordingly, system or network architectures have changed to compensate for a main storage which is relatively slow as compared to the processing devices. Cache memories and other techniques have been employed, in an attempt to uncouple the processors from the memory cards in main storage.
In connection with modifying data that resides in main storage, the traditional operation involves fetching the data from memory arrays to an internal register in a processor, modifying the data bits as required within the processor, then writing the modified data back into the memory arrays. This operation involves substantial system overhead. For example, the interface to main storage must be arbitrated for and acquired twice, once for a data fetch and once for storing data back into memory. If the interface is shared by multiple processors and by multiple cards of main storage, the time consumed in waiting for access to the interface is increased. A processor, upon gaining access to a particular memory card, must wait for the card to access its arrays to retrieve the data to be modified.
Techniques to more efficiently modify data in a memory are known. For example, U.S. Pat. No. 4,570,222 (Oguchi) discloses a data processing system with an information correcting function including a dynamic random access memory, a changing unit, a designating unit and a controller. The changing unit receives data from the RAM, and a selected portion of the data is modified within the changing unit, based on input from the designating unit.
In connection with color graphics displays, U.S. Pat. No. 4,016,544 (Morita et al) discloses a memory write-in control system, including a buffer memory for separately storing red, green and blue information for each of a multiplicity of dots. Each individual color unit receives a color designating input and a mask input from a write-in control unit which is controlled by a processor. If the mask bit is a logical one, the content is modified, while a logical zero in the mask bit leaves the corresponding contents unchanged.
There remains, however, a need to more effectively utilize processing devices, as well as a data bus joining multiple processing devices and main memory.
Therefore, it is an object of the present invention to provide a data processing system in which data in main storage is modified with substantially reduced use of an interface between main storage and multiple processors.
Another object of the invention is to transfer some of the logic circuitry involved in data modifying operations from the processors to the memory cards of main storage.
Another object is to increase the speed at which data modifying functions, including set and reset, are performed.
Yet another object is to provide a data processing system in which set and reset functions are performed on selected data in memory arrays, with just one access to the arrays being sufficient for these functions.